It is known to construct EEPROM cells having oxide/nitride/oxide stacks that form floating gate electrodes. Typical of such recent EEPROM structures is that shown by T. Y. Chan, K. K. Young and C. Hu, "A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device", IEEE Electron Device Letters, Vol pp. 93 et seq. (March, 1987). In this device, a source region and a drain region are formed in a semiconductor substrate, as separated by a gate region. An oxide-nitride-oxide sandwich layer is formed over the gate region to bridge the source and drain regions The memory is programmed by channel hot electron injection and the charges are stored in the oxide-nitride-oxide gate dielectric. The injection and storage of electrons and holes are confined to a short region near the drain. The portion of the channel near the source allegedly maintains the original positive threshold voltage, even after repeated erase operations. This construction obviates the need for a separate select transistor.
The above structure has, however, the disadvantage of introducing the possibility of oxide-nitride-oxide (ONO) traps near the source end of the cell. Were the nitride layer to store holes near the source end, the gate region would have a tendency to be rendered conductive across its length, as the threshold voltage would be lowered. This in turn could prevent the select transistor portion of the cell from ever turning off. Also, during read operations, if electron trapping were to occur near the source end, the gate region would have a tendency to be rendered nonconductive across its length, as the threshold voltage would be increased. This in turn could prevent the select transistor portion of the cell from ever turning on. Therefore, a need has arisen in the industry for an oxide-nitride-oxide integrated EEPROM structure that eliminates the possibility of such ONO traps.